“There are many applications of waveform generators in life, and many companies have various waveform generator products. You may be a little unfamiliar with waveform generators, because even though there are many applications of waveform generators, the general professional people rarely come into contact with waveform generators. In order to improve everyone’s understanding of the waveform generator, this article will introduce the design scheme of the AD9833 high-precision programmable waveform generator.
There are many applications of waveform generators in life, and many companies have various waveform generator products. You may be a little unfamiliar with waveform generators, because even though there are many applications of waveform generators, the general professional people rarely come into contact with waveform generators. In order to improve everyone’s understanding of the waveform generator, this article will introduce the design scheme of the AD9833 high-precision programmable waveform generator. If you have some interest in what this article is about to discuss, you may wish to continue reading.
1. Introduction of AD9833 waveform generator
The AD9833 is a low power, programmable waveform generator capable of generating sine, triangle, and square wave outputs. The waveform generator is widely used in various measurement, excitation and time domain response fields. AD9833 does not require external components. The output frequency and phase can be programmed by software, which is easy to adjust. The frequency register is 28 bits. When the main frequency clock is 25MHz, the accuracy When the main frequency clock is 1MHz, the accuracy can reach 0.004Hz.
Data can be written into AD9833 through 3 serial ports, the maximum operating frequency of these 3 serial ports can reach 40MHz, which is easy to be compatible with DSP and various mainstream microcontrollers. AD9833 operating voltage range is 2.3V-5.5V.
AD9833 also has a sleep function, which can make the unused part sleep and reduce the current consumption of this part. For example, if the AD9833 output is used as the clock source, the DAC can be put to sleep to reduce power consumption. The circuit uses a 10-pin MSOP type surface mount package, small size.
The main features of AD9833 are as follows:
Frequency and phase are digitally programmable;
When the working voltage is 3V, the power consumption is only 20mW;
The output frequency range is 0MHz-12.5MHz;
The frequency register is 28 bits (under the reference clock of 25MHz, the precision is 0.1Hz);
Can choose sine wave, triangle wave, square wave output;
No external components are required;
3-wire SPI interface;
The temperature range is -40℃-+105℃.
Second, the structure and function of AD9833
2.1 Circuit structure
AD9833 is a fully integrated DDS (DirectDigitalFrequencySynthesis) circuit that only needs an external reference clock, a low-precision resistor and a decoupling capacitor to generate a sine wave up to 12.5MHz. In addition to generating RF signals, the circuit is also widely used in various modulation and demodulation schemes. These schemes are all used in the digital field, and the use of DSP technology can simplify the complex modulation and demodulation algorithm, and it is very accurate.
The internal circuits of AD9833 mainly include numerically controlled oscillator (NCO), frequency and phase regulator, SineROM, digital-to-analog converter (DAC), and voltage regulator. Its functional block diagram is shown in Figure 1.
The core of AD933 is a 28-bit phase accumulator, which consists of an adder and a phase register. Every time a clock comes, the phase register increases by step size, and the output of the phase register is added to the phase control word and then input to the sine lookup table address. middle. The sine look-up table contains the digital amplitude information of a period sine wave, and each address corresponds to a phase point in the range of 0°-360° in the sine wave. The look-up table maps the input address phase information into a digital signal of sine wave amplitude, and then goes to the DAC to output the analog signal. The phase register returns to the initial state after every 228/M MCLK clocks, and the corresponding sine look-up table returns to the original state after a cycle. The initial position, so that a sine wave is output. The output sine wave frequency is:
Among them, M is the frequency control word, which is given by external programming, and its range is 0≤M≤228-1.
The VDD pin supplies power for the analog and digital parts of the AD9833, and the supply voltage is 2.3V-5.5V. The working voltage of AD9833 internal digital circuit is 2.5V, and the voltage regulator on its board can generate 2.5V stable voltage from VDD. Note: If VDD is less than or equal to 2.7V, the pin CAP/2.5V should be directly connected to VDD.
2.2 Functional Description
AD9833 has 3 serial interface lines, which are compatible with SPI, QSPI, MI-CROWIRE and DSP interface standards. Under the action of the serial port clock SCLK, the data is loaded into the device in 16-bit mode. The timing diagram is shown in Figure 3. , FSYNC pin is the enable pin, level-triggered, active low. When performing serial data transmission, the FSYNC pin must be set low, pay attention to the minimum value of the setup time t7 from FSYNC valid to the falling edge of SCLK. After FSYNC is set low, the data is sent to the input shift register of AD9833 on the falling edge of 16 SCLKs. FSYNC can be set high on the falling edge of the 16th SCLK, but pay attention to the data from the falling edge of SCLK to the rising edge of FSYNC. Hold the minimum and maximum value of time ts. Of course, you can also load multiple 16-bit data continuously when FSYNC is low, and set FSYNC high only on the falling edge of the 16th SCLK of the last data. The last thing to note is that when writing data The SCLK clock is a high and low level pulse, but when FSYNC first becomes low, (when data is about to be written), SCLK must be high (note the parameter of t11).
When the AD9833 is initialized, in order to prevent the DAC from producing false output, RESET must be set to 1 (RESET will not reset the frequency, phase and control registers), until the configuration is completed, and RESET is set to 0 when output is required; 8 after RESET is 0 -9 MCLK clock cycles to observe the waveform at the output of the DAC.
AD9833 writes data to the output and gets a response. There is a certain response time in the middle. Every time the frequency or phase register is loaded with new data, there will be a delay of 7-8 MCLK clock cycles before the waveform of the output changes. , There is an uncertainty of 1 MCLK clock cycle, because when the data is loaded into the destination register, the position of the rising edge of MCLK is uncertain.
Three, AD9833 pin function and timing
The pin arrangement of AD9833 is shown in Figure 2, and the function description of each pin is shown in Table 1.
The timing characteristics of the AD9833 are shown in Figure 3, Figure 4, and Table 2.
Fourth, the internal register function of AD9833
AD9833 has 5 programmable registers, including 3 16-bit control registers, 2 28-bit frequency registers and 2 12-bit phase registers.
4.1 Control Register
The 16-bit control register in the AD9833 is used by the user to set the desired function. Except for the mode selection bit, all other control bits are read and acted by AD9833 at the lower edge of the internal clock MCLK. Table 3 shows the function of each bit of the control register. To change the content of the AD9833 control register, the D15 and D14 bits must be both 0.
4.2 Frequency register and phase register
AD9833 contains 2 frequency registers and 2 phase registers, and its analog output is
Where: FREQEG is the frequency word in the selected frequency register, the signal will be phase shifted:
Among them, PHASEREC is the phase word in the selected phase register.
The operation of the frequency and phase registers is shown in Table 4.
5. Application Design
AD9833 can be used in the detection box matched with the L15 aircraft control box. The AD9833 can be used to generate a sine wave with adjustable frequency to simulate the speed signal of the wheel speed sensor, so as to check whether the brake anti-skid channel of the control box can be properly braked and anti-skid. detection.
5.1 Hardware circuit connection of AD9833
The detection box is designed with TI’s TMS320LF2407A DSP as the core controller. The application requires two speed signals, so the detection box needs to provide two independently adjustable frequencies. Figure 5 shows the hardware connection between TMS320LF2407A and AD9833.
The output of the external active crystal oscillator is sent to two AD9833 as the main frequency clock. The SPI port of the DSP adopts the active working mode, that is, the SPISIMO port is used to send data. In order to match the timing of the AD9833, the interface clock of the DSP (SPICLK signal) The mode selects the falling edge with delay, IOPC3 and IOPC5 are used as circuit strobe signals, U2 is strobe when IOPC3 is low level, and writing data to U1 is invalid at this time; Similarly, U1 is strobe when IOPC53 is low level, this When writing data to U2, it is invalid.
5.2 Software Programs
Figure 6 shows the software flow of the AD9833.
Whether writing the control register, the frequency register or the phase register, the strobe signal needs to be set to a valid state before writing data, so that the written data will be valid, otherwise it will be invalid. The SPI interrupt request will be generated after the DSP sends a data word. The interrupt method is not used in this design, and the interrupt flag is checked to jump out, and the receive buffer of the DSP is dummy read to clear the interrupt flag.
The Links: NL6448AC33-27 2MBI400L-060