“As the industry moves to DDR5 development, test and production, new hardware and software tools are required to address the latest challenges posed by DDR5 testing. Tektronix has developed a range of high bandwidth oscilloscopes and probes to acquire signals from DDR5 devices, as well as powerful software tools for verification. Visit Tek.com to learn more about our solutions, watch video demos or webinars related to DDR5 and Tektronix solutions.
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Author: Tektronix
The world is going through an unprecedented era of explosive growth in data, a trend that is expected to accelerate further as new technologies are implemented on a wider scale. Typical examples include: next-generation wireless communications in the form of 5G, the expanding field of artificial intelligence and machine learning, the Internet of Things (IoT), cryptocurrencies, virtual reality, and even automobiles. Throughout 2021, 44 trillion gigabytes (440 trillion gigabytes) of data are expected to be generated, with an estimated 1.7MB of data generated per second per person on Earth. Such a huge amount of data needs to be stored, accessed and analyzed faster than ever before, which requires the system to have higher bandwidth, higher storage density, and higher overall performance.
Faster memory brings new challenges to DDR5 testing
To cope with the ever-increasing amount of data being generated, it is necessary to increase memory performance to store, transfer and process all this information. The main bottleneck in this process is the speed at which memory can access and transfer data. Memory access times are slow, causing overall system performance to lag, and data throughput itself is limited by the transfer rate of memory. Historically, the dominant form of high-performance, fast-access memory has been Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). DDR SDRAM was introduced as a standard in the 1990s. After its introduction, it has developed rapidly. In 2014, the fourth-generation standard, DDR4, was launched. DDR4 is a memory interface with an initial data transfer rate of 1600 MT/s, which eventually reached 3200 MT/s as the standard matured. This was enough when the computer processor had only 8 cores, but with the advent of today’s 28-64 core multi-core processors (expected to reach 80C 96 cores in the future), it is clear that we need memory performance that is beyond the capabilities of DDR4 .
To help meet this demand, the industry is migrating from DDR4 to the next-generation DDR memory standard, DDR5. DDR5 will succeed the previous generation standard as the dominant fast-growing standard. Based on DDR4, DDR5 will provide a transfer rate of 3,200 MT/s initially, up to 6,400 MT/s, and is expected to expand to up to 8,400 MT/s in the future.
DDR5 presents a whole new set of challenges that must be overcome during implementation and verification. Higher data rates will expand the required test equipment bandwidth, require new procedures to measure jitter that cannot be measured by previous methods, require new DDR units in the form of receiver equalization, and even introduce new standardized tests using fixtures. is a major challenge for DDR5 verification.
SOLUTION: Tektronix Oscilloscopes and TekEXPRESS DDR TX Software
The improved performance of DDR5 means that higher performance equipment is required to analyze and test DDR5-enabled devices. To meet this performance requirement, Tektronix has developed an in-depth solution that utilizes high bandwidth oscilloscope and probe hardware, such as the DPO71604SX and P7716, along with a new software automation platform.
Figure 1. Tektronix tools used in the DDR5 test solution.
Tektronix TekExpress DDR Transmitter (Tx) software is a purpose-built automated test application to verify and debug DDR5 devices according to the parameters specified in the JEDEC (Joint Electronic Device Engineering Council) specification. Tektronix Option DDR5SYS (TekExpress DDR Tx) includes the following full test coverage and multiple debug tools:
• DRAM components
• Data buffer/RCD element
• System board
• Embedded Systems
• Server and Client/Desktop
TekExpress DDR Tx supports measuring over 50 DDR5 electrical and timing parameters according to the DDR5 JEDEC specification. It has built-in powerful tools to assist in characterization and debugging, such as multi-gating capabilities, DDR5 DFE analysis software, and user-defined acquisition modes that give the user full control over test conditions.
Tektronix TekExpress DDR Tx solutions have several unique and innovative features that reduce the effort spent in testing and speed up the DDR system and device testing process. TekExpress DDR Tx provides an easy-to-use interface with simple step-by-step operations to speed up the testing process.
Steps used in testing and memory circuits
Customers can use the following steps to verify that a product meets the DDR5 specification:
Solder a high impedance Tektronix probe to the DDR subsystem to be tested, allowing access to the electrical signals of interest.
2. TekExpress DDR Tx software analyzes the detected signal and compares it with the DDR5 specification. Other software running on the oscilloscope can be used to perform various tests such as drawing eye diagrams and measuring relevant electrical parameters.
Figure 2 is an example of using a probe to access the device to perform system-level TX testing. In this example, the system-on-chip (SOC) communicates with the device under test (DRAM/RCD/DB) to transmit bidirectional traffic over the DDR bus. The user accesses the interface using an interposer soldered under the DRAM, and probes the interface using a high impedance probe amplifier. TekExpress DDR Tx software provides the necessary tools to measure various parameters such as clock jitter, read/write timing, and even eye diagrams.
Figure 2. System-level TX testing.
3. At the end of the test, a test pass/fail report is generated, providing details such as comparison with the device under test, physical setup, parameters under test and JEDEC specifications.
4. If an indicator fails the test, or an unexpected result occurs, you can further use the TekExpress DDR software solution to debug the result.
DFE receiver equalization and signal de-embedding using Tektronix SDLA64
Increasing signaling speeds and shrinking form factors have created multiple challenges for next-generation multi-gigabit design and test methods. The smaller the shape, the more difficult the signal access is, and the obtained detection point will be unsatisfactory, which will lead to the loss and reflection of the acquisition signal, because there is no impedance breakpoint in the ideal measurement position.
With the advent of DDR5, the tools previously used for DDR testing and debugging have become inadequate. Designs with higher data rates and more stringent load requirements make smooth access to the signal not impossible, but it will certainly become extremely difficult. One of the effective ways to solve these problems is to use the Tektronix Serial Data Link Analysis (SDLA) software package. With the SDLA feature, the user can remove the loading effects of the test setup (probes, interposers, cables) through the de-embedding process. Whether it’s reflections, insertion losses, cross-coupling, or other impairments, SDLA provides powerful capabilities to efficiently analyze signals as if these effects weren’t there. This can greatly improve the validity and accuracy of the measurements obtained, and can even directly determine whether the device will pass the test.
Tektronix DFE Analysis Software
Receiver equalization was introduced for the first time in DDR in the form of 4th-order DFE (Decision Feedback Equalization). This presents additional challenges when accessing and analyzing DDR5 signals. For example, the resulting eye diagram may remain closed even after de-embedding (Figure 3). To further open the eye diagram, DFE equalization must be achieved.
Tektronix has developed various tools to help solve the problems DFE introduces during testing. Using SDLA, the DFE gain and order values can be trained by analyzing a continuous stream of data from the device. The DFE feature can then be used to input the TekExpress DDR Tx automation software to generate the eye diagram after applying the DFE on the burst signal. A stand-alone DFE application (standard with TekExpress DDR Tx) is also available, where the user can manually generate and view DDR signals after applying DFE equalization outside of the automation framework.
Figure 3. Example of opening eyes in an eye diagram.
Jitter Noise Floor Calibration
DDR5 imposes new Rj/DJ jitter measurement requirements for CLK, DQS, and DQ. Also, the Rj metric is around 0.5ps (very strict). Tektronix has developed a new jitter noise floor noise calibration technique that can be used directly on Tektronix oscilloscopes. The tool provides an option to include probe, probe tip and de-embedding filter files during noise calibration to account for additionally generated or amplified noise. The tool is fully integrated with oscilloscope analysis software (DPOJET) to remove oscilloscope noise jitter from the measurement results.
Summarize
As the industry moves to DDR5 development, test and production, new hardware and software tools are required to address the latest challenges posed by DDR5 testing. Tektronix has developed a range of high bandwidth oscilloscopes and probes to acquire signals from DDR5 devices, as well as powerful software tools for verification. Visit Tek.com to learn more about our solutions, watch video demos or webinars related to DDR5 and Tektronix solutions.
The Links: NL8060BC31-42G MG15Q6ES1
