“A design and implementation method of an evolvable IP core is proposed. This IP core adopts the design idea of evolutionary hardware, and applies genetic algorithm to the design of hardware circuit, so that the circuit can automatically time the internal circuit according to the current environment, so as to generate the most effective circuit, and can be used in ordinary FPGA. implemented on the device. The evolvable IP core is expressed in the form of HDL source code, which is the same as the multiplexing method of the common IP core, and can be integrated into different target reconfigurable devices, which greatly reduces the design time of complex systems and improves the utilization of the design. High efficiency is a promising development direction for evolvable hardware.
Authors: Zong Ping, Zhou Yedan
A design and implementation method of an evolvable IP core is proposed. This IP core adopts the design idea of evolutionary hardware, and applies genetic algorithm to the design of hardware circuit, so that the circuit can automatically time the internal circuit according to the current environment, so as to generate the most effective circuit, and can be used in ordinary FPGA. implemented on the device. The evolvable IP core is expressed in the form of HDL source code, which is the same as the multiplexing method of the common IP core, and can be integrated into different target reconfigurable devices, which greatly reduces the design time of complex systems and improves the utilization of the design. High efficiency is a promising development direction for evolvable hardware.
With the rapid development of information technology, the problems faced by computer systems are becoming more and more complex, and how to ensure the reliability of complex systems has become a problem that cannot be ignored. Evolvable hardware provides us with a good solution. Evolvable Hardware EHW (Evolvable Hardware) is a new genre of hardware research that combines evolutionary algorithms and programmable logic elements. When the environment in which it is used changes, or is placed in an unknown environment, the hardware automatically changes its internal structure so that it is always in the most suitable state to complete the specified tasks quickly and efficiently.
Programmable gate array (FPGA) is used as a hardware evolution platform by most foreign researchers due to its unique advantages. EHW utilizes FPGA’s online programmable technology (ISP) and dynamic reconstruction technology, takes the configuration information of FPGA as chromosome, and performs repeated fitness calculation, crossover and mutation through Genetic Algorithm (GA), and finally evolves the symbolic environment requirements individual (i.e. circuit configuration) so that the circuit adapts to changes in the environment.
At the same time, with the development of FPGA technology, the performance of chips is getting stronger, the scale is getting bigger and the development cycle is getting longer and longer, which makes the chip design industry face a series of new problems: the design quality is difficult to control, Design costs are also getting higher. IP (Intelligence Property) technology solves the challenges faced by today’s chip design industry. IP refers to the logic function blocks that can be used to generate ASIC and PLD, also known as IP core (IP Core) or virtual device (VC). Designers can reuse the IP cores that have been designed and verified, so as to focus on the design of the entire system, improve the efficiency and correctness of the design, and reduce costs. At present, the digital IP has been fully developed, and the IP core can be easily purchased and integrated into the SoC design.
Therefore, it can be considered to apply the idea of evolutionary hardware to the design of IP cores, design an evolvable IP core, evolve corresponding circuits according to the current environment, and implement them in common reconfigurable devices.
1 What is an evolvable IP core
From experience with evolutionary hardware, usually only one part of the system is adaptive (evolvable), and the other part can be implemented by traditional immutable circuits. Similarly, some IP cores are evolvable and some IP cores are immutable in systems constructed using IP cores. Those IP cores that are evolvable are called evolvable components or evolvable IP cores.
Evolvable IP cores are stored in the component library like normal IP cores, and after being downloaded and placed in a reconfigurable device, they will automatically evolve their internal circuits. Evolvable IP cores can be removed from reconfigurable devices when adaptive behavior is no longer required. Evolvable IP cores and common IP cores are reused in the same way.
2 General Architecture of Evolvable IP Cores
As shown in Figure 1, the evolvable IP core is composed of reconfigurable circuits, gene units and controllers (in this paper, a reconfigurable circuit refers to a part of the evolvable IP core; a reconfigurable device refers to the entire reconfigurable IP core). platform such as FPGA). It should be emphasized here that the gene unit does not contain fitness calculation, it only realizes the operation of genes, chromosome storage and fitness storage. The computation and environment for fitness is provided by other cores. The genetic unit generates some configurations and uploads them to the reconfigurable circuit, and the environment evaluates these configurations and sends the fitness value to the IP core. The Evolvable IP core is actually a circuit generator controlled by the environment.
The communication between the environment (proposed by other cores) and the evolvable IP core is as follows: first the IP core is initialized (generating an initialization population), and then enters an infinite loop as follows – when the environment changes, the environment calculates the fitness of the current circuit configuration , and determine whether the circuit adapts to the environment. If the configuration in the chromosome memory is not available, a control message is sent to the IP core and the IP core begins to evolve. That is, the genetic unit takes the hardware configuration information as a chromosome, and performs genetic operations such as crossover and mutation according to the fitness to generate a new population. The environment calculates the fitness of the new population and determines whether there are individuals (configurations) that satisfy the current environment. If not, send control information to the IP core, and the genetic unit continues to evolve the circuit configuration until there is a configuration that meets the current environment; if there is, send the fitness value to the IP core, and the IP core uses this newly generated optimal configuration to reconfigure the reconfigurable circuit and save the current optimal configuration and its fitness value in the chromosome memory, waiting for the next request from the environment.
The environment always requires downloading the current optimal evolution circuit, therefore, the IP core must save the optimal configuration so far and provide it when needed. Evolvable IP cores always shield the refactoring process, so it is invisible to the external environment.
For some special applications, dedicated evolvable IP cores must be developed for them, because the architecture of gene units and reconfigurable circuits reflecting the requirements of the application will make the evolution process better than a random search. Since the fitness calculation is performed outside the IP core, the IP core supports in principle dynamic fitness functions and infinite evolution. Evolvable IP cores can be implemented in software.
3 Implementation of Evolvable IP Core
3.1 Problems in Implementation
There are usually three types of reusable IP cores: soft core, solid core and hard core. This article is about soft cores. The goal of this paper is to design and implement an evolvable IP core expressed in HDL source code (eg, VHDL). The advantage is that the representation of IP cores is platform independent, so that they can run in a variety of different target structures. The main problem to solve is the automatic reconfiguration of the internal reconfigurable circuits of the evolvable IP cores (since they are evolvable).
When an evolvable IP core is downloaded from a component library to a specified location in a reconfigurable device, its internal reconfigurable circuitry must be reconfigured. This means that some programmable blocks in the reconfigurable device must be able to configure other internal programmable blocks of the reconfigurable device. In addition, the evolvable IP core (its gene unit) can be placed anywhere in the programmable array (ie, the reconfigurable device), that is, the reconfigurable device must support internal reconfiguration.
FPGA, with its advantages of dynamic reconfiguration, is undoubtedly the best implementation platform for evolving IP cores. However, normal FPGAs do not support internal reconfiguration, but only allow external reconfiguration through a special configuration interface (see Figure 2). Currently, there is only one platform that supports internal reconfiguration, the cell array, but such chips are still quite rare. Therefore, in order to realize the evolutionary IP core in the common FPGA device and make it play a role in practical application, some other methods must be adopted. Hardware virtualization is a common design technique for FPGA-based systems. Starting from this idea, this paper adopts a technique called virtual reconfigurable circuits to realize internal reconfigurable circuits in evolvable hardware. However, the concept of designing virtual reconfigurable circuits is extended in this paper.
3.2 Virtual Reconfigurable Circuits
Some FPGA chips support partial reconfiguration, which allows part of a reconfigurable system to be reconfigured without affecting the operation of the rest. The advantage of a partial refactoring is that it takes less time to refactor than a full refactoring. This article takes the Xilinx Virtex FPGA that supports partial reconfiguration as an example to illustrate the realization of virtual reconfigurable circuits. IP cores can be dynamically downloaded to or deleted from the FPGA. All operations are done through the Virtex refactoring port and Jbits interface. When an evolvable IP core is downloaded, its reconfigured bit string constructs the following units at specified locations; virtual reconfigurable circuits, gene units, and controllers.
The advantage of this approach is that programmable element arrays, routing circuits, and configuration memory can be designed exactly according to specific application needs. The reconstruction mode and granularity of virtual reconfigurable circuits can accurately reflect the needs of specific applications. With virtual reconfigurable circuits, it is easy to insert domain knowledge into the architecture of gene units and reconfigurable circuits, thereby obtaining accurate realizations of circuit software models.
Figure 3 shows an example of a virtual programmable element. This virtual reconfigurable circuit consists of 8 such elements, with 4 inputs and 2 outputs. These virtual programmable elements are called reconfigurable functional blocks (CFBs). Each CFB corresponds to a configuration bit string (the bit string here is 6 bits), two of which determine the function of the CFB, and the other four bits define the input connection information. The routing circuit consists of multiplexers, which are controlled by bit strings in the configuration memory. The configuration memory consists of Virtex cells, and a Virtex cell contains two flip-flops for storing two bits in the configuration bit string. All bits of the configuration memory are connected to a multiplexer, which controls the routing and selection of functions in the CFB.
The number of CFBs in a virtual reconfigurable circuit depends on the specific application. Virtual reconfigurable circuits are described at the structural level VHDL, but some basic circuits (eg “MAX” circuits) are described at the behavioral level. Virtual reconfigurable can be synthesized under different target devices, and the target device does not need to support partial reconfiguration.
3.3 Gene units and controllers
There are usually two options for the realization of the gene unit and the controller: to use a common microprocessor to realize, or to design a dedicated circuit to realize it.
A dedicated circuit refers to a hardware implementation of an evolutionary algorithm, and many such implementations have been developed in the field of evolvable hardware. The advantage of this algorithm is that the circuit evolves quickly and is suitable for complex applications.
When implemented with a microprocessor, ready-made microprocessor soft cores can be purchased or obtained free of charge, such as the MicroBlaze and PicoBlaze microcontroller IP cores provided by Xilinx, the Nios core produced by Altera, and so on. Additionally, an on-chip processor can be used if the target reconfigurable device is given, and the Xilinx Virtex II Pro XC2VP50 chip contains four PowerPC processors. Processors must be programmed to execute programs that communicate with the environment around the nucleus and perform genetic manipulation of chromosomes. In addition, the processor is also responsible for the reconfiguration of the internal virtual reconfigurable circuits.
This paper defines a new level of abstraction for digital system design and introduces a component approach to the design of evolvable hardware. To implement an evolvable IP core, a virtual reconfigurable circuit is used. This approach is slightly more expensive in terms of the number of gates, but can greatly speed up the evolution of hardware.
Evolvable IP cores are designed primarily to achieve adaptable and high-performance real-time systems at a reasonable cost, most commonly such as image compression. The structure and interface of the core proposed in this paper are only the most basic, and can be extended in practical applications. For example, the core can also be extended with a read configuration port, which is necessary for some applications. Or include two virtual reconfigurable circuits RC1 and RC2 in the evolvable IP core. RC1 realizes the current optimal evolution circuit. Circuit evolution is done in RC2. If a better circuit evolves in RC2, its configuration is fed into RC1, which then presents the best response to the changing environment in the form of a series of digital circuits.
Compared with previous methods, the method proposed in this paper is more adaptable and portable. Evolvable IP cores are expressed in the form of HDL source code, which is easy to reuse and modify. In addition, the evolved configuration bit string can also be reused in other applications as a variant IP core. The evolvable IP core shortens the circuit design time, improves the design utilization, and promotes the development of evolvable hardware towards practicality.
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