Rapidly advancing applications such as artificial intelligence and autonomous driving place higher demands on the performance of next-generation integrated circuits (ICs). For IC engineering teams, larger IC designs and greater complexity also mean a corresponding increase in test time and cost, as well as the engineering effort required to plan and deploy DFT structures and functions in each design will also grow.
To help chip test teams address these challenges, Mentor, a Siemens business, introduced Tessent™ Streaming Scan Network technology into its Tessent™ TestKompress™ software. The solution includes embedded infrastructure and automation to isolate module-level DFT requirements from test resources available at the top level, enabling a no-compromise, hierarchical DFT process, greatly simplifying DFT planning and implementation, while reducing test time 4 times shorter. This solution fully supports repeating cell designs and is optimized for the same core, making it ideal for increasingly large and emerging computing architectures.
Brady Benware, vice president and general manager of Chip Lifecycle Solutions at Mentor Tessent, said: “The complexity of IC test continues to increase as design sizes, advanced technology nodes, and usage model requirements continue to increase, placing serious demands on IC design teams. challenges. With the new Tessent Streaming Scan Network, our customers are able to reduce the workload of test implementation while reducing the cost of test and preparing their designs for the future.”
Tessent Streaming Scan Network technology adopts a bus-based scan data distribution architecture, which can test any number of cores at the same time, achieve high-speed data distribution, efficiently solve the imbalance between cores, and perform analysis on any number of the same cores at a fixed cost. test, which greatly reduces the test time. The technology also provides a plug-and-play interface in each core that simplifies timing closure of scans, ideal for docking repetitive units.
The solution consists of interconnecting a series of host nodes in each design module. Each host distributes data between the network in the module and the test fabric. The software automates the process of implementation, vector generation, and fault reverse mapping. DFT engineers can fully optimize DFT test resources for each module without worrying about affecting other parts of the design, which will help reduce implementation efforts quantity. At the same time, the solution also significantly reduces the amount of test data and shortens the test time by optimizing the processing of the same core, eliminating the waste of test data, and time-division multiplexing.
“By introducing Tessent Streaming Scan Network technology in Tessent TestKompress, we are able to provide customers with a scalable test access solution for today’s and tomorrow’s advanced IC designs,” said Sangyun Kim, vice president of Samsung Electronics Design Technology Team. The Tessent Streaming Scan Network can make complex designs highly testable without a lot of effort.”
The addition of the Tessent Streaming Scan Network capability to the Tessent TestKompress product is the result of more than a decade of research and development by Mentor in advanced hierarchical DFT implementation and test data bandwidth management, which Mentor has developed in conjunction with several leading semiconductor manufacturers.
The Tessent Streaming Scan Network is fully compatible with other Tessent DFT products and can be combined with Tessent Diagnosis’ cell-aware and layout-aware diagnostic capabilities to provide an end-to-end defect detection and diagnosis solution. All Tessent DFT products are part of the Tessent Safe ecosystem with a full set of certified ISO 26262 documentation available for all ASIL ISO 26262 projects.
For more information on Tessent Streaming Scan Network technology, visit www.mentor.com/tessent
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