“AC plasma Display panels (PDPs) are called “plasma” displays because they use small cells that contain a charged ionized gas (ie, plasma). This white paper discusses the use of optocouplers and opto-isolated gate drivers in AC PDPs. It also discusses the fundamentals of AC plasma Display panels and the different design considerations used in their applications.
AC plasma display panels (PDPs) are called “plasma” displays because they use small cells that contain a charged ionized gas (ie, plasma). This white paper discusses the use of optocouplers and opto-isolated gate drivers in AC PDPs. It also discusses the fundamentals of AC plasma display panels and the different design considerations used in their applications.
A plasma display panel (PDP) is essentially a matrix of tiny fluorescent tubes that are controlled in complex ways. There are two main types, DC and AC. AC PDP is the most commonly used method due to its simpler structure and longer service life.
Fundamentals of AC Plasma Display Panels
The basic display cell (shown in Figure 1) consists of a pair of sustain electrodes Xi and Yi surrounded by a dielectric. Address electrodes Aj are located on opposite Glass substrates and extend perpendicular to electrodes Xi and Yi. The battery is filled with a mixture of neon and xenon gas that ionizes when the applied voltage exceeds its breakdown voltage. When accelerated under a high-voltage electric field, positively charged ions and negatively charged electrons collide. This collision produces ultraviolet photons, which excite the phosphors to emit visible light. For color plasma display panels where the phosphors are susceptible to damage by positive charges, the discharge is mainly controlled between the Xi and Yi electrodes to avoid direct impact of charges on the phosphors deposited on top of the address electrodes Aj.
basic display unit
Such a unit has only two states: ON and OFF. In order to display 256 grayscales, a frame is divided into eight subframes using the ADS (Address-Display-Separation) method, and the ratio of the display period of the subframes is 1:2:4:8:16:32:64:128 . The display intensity can be set to any of 256 brightness levels by selecting the appropriate subframe combination.
Displaying a subframe of an image involves three phases (reset, write and sustain). In the reset phrase, the cell is initialized and the wall charges are cleared. In the write phrase, a subframe of data is written into the panel through a write discharge to accumulate wall charges in the selected cells. In the sustain phrase, sustain pulses are applied alternately to all X and Y electrodes to discharge the AC current in the panel and display the image.
A simplified representation of the electrode drive waveforms is shown in Figure 2. Vreset is a reset pulse, Va represents image data, -Vsc is a line scan pulse, and Vsus is a display sustain pulse.
The timing distribution diagram of ADS technology is shown in Figure 3. Each subframe is driven by reset, write and sustain phases as shown.
In the NTSC system, the video image is refreshed at 60 Hz and each frame lasts 16.7 ms. There are a total of 512 sustain pulses in each frame, two in the first subframe. If each sustain pulse lasts 5 µs, the total time for one frame display period is 2.6 ms. The remaining 14.1 ms are reserved for reset and write cycles. The reset and write cycles in each subframe should be 14.1 ms / 8 = 1.8 ms. If the reset cycle takes about 50 µs, the write cycle will take 1.75 ms, during which all rows must be scanned. For a high-resolution large-panel display involving 1920 x 1080 pixels, 1080 lines need to be scanned in 1.75 milliseconds. Therefore, the maximum pulse width of the line scan pulse is 1.75 ms / 1080 = 1.6 µs.
Basic Electrode Drive Waveforms
ADS timing allocation diagram
For high-Contrast and high-brightness images, best results are obtained when the light is emitted only during the sustain phase, and this phase should be as long as possible. However, both reset pulses and write pulses cause discharges that reduce contrast. Studies have shown that brightness is proportional to the rise and fall times of the drive pulses. The slow ramp of the reset pulse reduces the brightness produced by this undesired discharge and improves image contrast. Speeding up the ramp-up of the sustain pulse and increasing the sustain period can enhance image brightness. This means that the cycle of the write phase should be as small as possible, as long as it does not cause any write defects. Many methods have been used for high-speed write operations without compromising image quality.
Panel drive circuit
The Electronic control and drive block diagram is shown in Figure 4.
The scan electrodes Yi controlled by the scan controller and driver run horizontally to sequentially scan the frame data lines. Electrodes Aj extend vertically to write column display data into the display cells at each intersection. One end of the electrode Xi running in parallel with Yi is connected and controlled by a common sustain driver to apply high voltage pulses to the entire panel to display image data.
PDP panel block diagram
Design Considerations for Scan Driver IC Interfaces
The scan driver includes several ICs capable of switching high voltages from the Vpwr node or the Vsub node to each output Yi, as shown in Figure 5.
Scan Driver Block Diagram
The scan driver IC floats on the Vsub node and can be switched between various potentials. Typically, optocouplers are required to level-shift data, clocks, strobes, and other control signals from the control logic circuit to the scan driver IC. The main considerations in choosing the right optocoupler are speed, power consumption, size, common-mode noise immunity, and fan-out capability.
If the scan pulse width is 1 µs, the data rate of the line scan signal is about 1 MBd, and for a 1 MBd data signal, the clock is 2 MBd. Because the data and clock signals travel in parallel across isolation boundaries, the propagation delay difference between the channels should be kept low to establish sufficient headroom for the data before the clock signal can safely latch it. Avago Technologies HCPL-0738 dual-channel and HCPL-0708 single-channel 15 MBd optocouplers, as well as HCPL-0630 or HCPL-0631 10 MBd dual-channel optocouplers, all feature maximum propagation delay skew to ensure channel-to-channel variance is less than 40 ns. Propagation delay skew is typically higher for Avago HCPL-0600 or HCPL-0601 single channel optocouplers. HCPL-0630/0631 have open collector outputs,
Plasma panel images show that charging and discharging involves high frequency, high current, which means a lot of power is drawn through the power switch. As isolation and level shifting devices for power electronics, optocouplers must be placed close to the power driver IC. This means that the ambient temperature of the optocoupler is typically high, around +70°C to +85°C. Ideally, the optocoupler should dissipate as little power as possible to keep the junction temperature of the LED and photodetector below a value that degrades performance or lifetime. The total power dissipation of the optocoupler can be calculated by the following formula:
PT = PLED + PDetector = PLED + PStatic + PSwitching
= IF (average) • VF + Vcc • Icc + CLoad • Vcc 2 • f
Total power dissipation is a function of steady state supply current, LED drive current, switching frequency and load capacitance. In a typical PDP scan drive application, the load is the capacitance of all gates being driven. Switching power is typically less than 10 mW at 1 MHz. At 50% on time, the average LED current is about 5 mA. Therefore, the power consumption of the LED is about 7.5 mW and the VF is about 1.5V. The main source of heat is the steady state power consumption of the detector. The HCPL-0738 has a maximum supply current of 16 mA, so the total detector power consumption is less than 80 mW. For the HCPL-0630/0631, the supply current is less than 11 mA, so the power consumption is less than 55 mW. The demand for high-resolution and large-size panel displays requires a higher number of driver ICs to be packaged in limited PCB board space, which means that the size of components in PDP drivers is becoming more and more critical. Avago Technologies dual-channel SO-8 optocouplers save at least 40% space compared to two single-channel devices.
The Links: LQ121S1LGF1 DMF5010NB-FW-BC