“The purpose of this lab activity is to examine the structure and operation of a Silicon Controlled Rectifier (SCR). SCRs are mainly used in devices that need to control higher power (at high voltage). SCRs are capable of switching high currents on and off and are suitable for medium and high voltage AC power control applications such as light modulation, voltage regulators and motor control. In addition, SCRs can be formed unintentionally in integrated circuits, and when they are triggered, they can cause circuit failure, even reliability issues and damage.
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By Doug Mercer, ADI Consulting Fellow, Antoniu Miclaus, Systems Applications Engineer, ADI
The purpose of this lab activity is to examine the structure and operation of a Silicon Controlled Rectifier (SCR). SCRs are mainly used in devices that need to control higher power (at high voltage). SCRs are capable of switching high currents on and off and are suitable for medium and high voltage AC power control applications such as light modulation, voltage regulators and motor control. In addition, SCRs can be formed unintentionally in integrated circuits, and when they are triggered, they can cause circuit failure, even reliability issues and damage.
The SCR is a 4-layer solid state current control device with three terminals. They have anode and cathode terminals like conventional Diodes, and a third control terminal, called the gate. SCRs are unidirectional devices: they carry current in only one direction, just like a Diode or rectifier. An SCR can only be triggered by current delivered to the gate; it combines the rectification function of a diode with the on/off control function of a Transistor.
SCRs are typically used in power switching applications. In the normally closed state, the device limits the current to leakage current. When the gate-to-cathode current exceeds a certain threshold, the device turns on and delivers current. As long as the current through the device is higher than the hold current, the SCR remains on even after the gate current is removed. Once the current falls below the holding current for a period of time, the device turns off. If the gate is pulsed and the current through the device is lower than the latching current, the device will remain off.
Figure 1b shows the 4-layer structure of the SCR and 3 terminals can be seen: one on the outer p-type layer, called anode A; the second on the outer n-type layer, called cathode K; and the third on the lower NPN The base of the transistor part, called gate G.
Figure 1. SCR Equivalent Circuit
As shown in Figure 1c, the SCR can be viewed as two separate transistors. The SCR equivalent circuit consists of a PNP transistor and an NPN transistor, and the two transistors are connected to each other, as shown in Figure 1d. As you can see, the collector of each transistor is connected to the base of the other transistor, forming a positive feedback loop.
SCR has two stable states. The first, the non-conducting off state. In the case where the gate terminal is turned on, it is first assumed that no current flows into the base terminal of the NPN transistor Q2. If the base current is zero, the collector current of Q2 is also zero. If the collector current of Q2 is zero, then the current flowing from the base of PNP transistor Q1 is zero. If Q1’s base current is zero, then Q1’s collector current should be zero. This is consistent with the initial assumption that the base current of Q2 is zero. Since both Q1 and Q2 have zero collector current (zero base current), it follows that the emitter current in either transistor should also be zero. This zero-current off state remains stable as long as any leakage current through Q1 or Q2 is very small from emitter to collector.
The second stable state is the on state. The SCR can be transitioned or switched from the off state to the on state by injecting a small amount of current into the gate terminal. Perform the same steps in this loop as you just did in the off state. It is not difficult to find that as long as the base current is supplied to Q2, there will be a larger collector current (which is the ß of the base currentNPNtimes) to start the transfer. This Q2 collector current will become the base current of Q1. This base current in Q1 produces a larger collector current in Q1 (ß of the base currentNPNtimes). The collector current of Q1 flows back to the base of Q2, further increasing its base current. After this current feedback loop is established, the initial gate current can be removed, and the SCR will remain on as long as the external circuit around the SCR provides current through the SCR. The only way to turn off the SCR is to reduce the current below the critical “hold” current level.
One thing to note about this positive feedback loop: the SCR will remain on and will remain in this latched state as long as the following conditions are met:
When the SCR is on, the voltage drop across the SCR from terminal A to K is Q1VBEand Q2VCESATsum, with Q2VBEand Q1VCESATThe sum is connected in parallel. We know that when the collector base junction is forward biased to the saturation region, that is VCEless than VBE, the ß of the BJT device drops. V for both transistorsCEwill decrease until the positive feedback gain equation is satisfied, and ßPNP × ßNPNequal to 1.
It is worth noting that the ß of a BJT transistor is also smaller when the collector current is small, according to the above equation, if the leakage current is small enough, resulting in ß at this low leakage current levelPNP × ßNPNless than 1, then the SCR will remain in the off state.
The ADALP2000 Analog Parts Kit does not contain SCRs, but the equivalent circuit shown in Figure 1d can be constructed using discrete PNP and NPN transistors to simulate SCRs.
Material
• ADI ADALM2000 Active Learning Module
• Solderless breadboard
• Two 1kΩ resistors
• Two 100kΩ resistors
• A 0.1µF capacitor
• One small signal NPN transistor (2N3904)
• A small signal PNP transistor (2N3906)
illustrate
Build the SCR equivalent circuit model shown in Figure 2 on a solderless breadboard.
Figure 2. Circuit used to simulate SCR
Two 100 kΩ resistors R1 and R2 are installed at each transistor’s respective VBEposition to ensure that any small leakage current does not trigger the simulated SCR by itself. Resistor R3 converts the voltage pulse from AWG2 to trigger current.
hardware setup
The breadboard connection for the SCR is shown in Figure 3.
Figure 3. Breadboard connections for simulating SCRs
procedural steps
AWG1 should be configured as a sine wave with a peak-to-peak amplitude of 10V, zero offset, and a frequency of 100Hz. AWG2 should be configured as a square wave with a peak-to-peak amplitude of 800mV, an offset of 400mV, and a frequency of 100Hz. Make sure to run both AWG channels at the same time.
Trigger the oscilloscope on channel 1. Observe the input sine wave on oscilloscope channel 1 and on oscilloscope channel 2 through RLvoltage, adjust the phase of AWG2 in 180° to 360° steps. Depending on the phase setting of the AWG2, the resulting curve may look like the following figure. It can be seen that by RLThe voltage of the SCR is zero, the SCR is in the off state, until the trigger pulse from AWG2, the SCR is in the on state until the input sine wave voltage exceeds zero.
Figure 4. Example of waveform
Figure 5. Scopy waveform example
When the SCR is on and delivering current, the voltage drop across the SCR is measured and reported.
By adjusting AWG2, find the minimum pulse voltage (amplitude) that can trigger the SCR. According to this voltage R3 and Q2’s VBE, to estimate the minimum trigger current. The result will be explained.
Try using larger values (1MΩ) and smaller values (10kΩ) for R1 and R2. How does the minimum trigger voltage change?
Replace resistor R3 with a 0.1µF capacitor. The coupling capacitor acts as a differentiator, converting the square wave pulse output from the AWG into narrow positive and negative current spikes on the rising and falling edges of the square wave. How does this affect when and how the SCR fires?
Inadvertently formed parasitic SCRs in integrated circuits
Applications utilizing SCR characteristics were discussed previously. Unfortunately, the formation of SCRs in integrated circuits may not be desired, and if these SCRs are triggered, they may cause circuit failure, and even lead to reliability problems and damage to the integrated circuit.
latch
Latch up is a potentially destructive condition. This condition triggers a parasitic SCR, shorting the positive and negative supplies. If the current is not limited, electrical overstress can occur. A typical latch-up situation occurs in CMOS output devices, when one of the two parasitic base-emitter junctions is temporarily forward biased during an overvoltage event, the driver transistor and well form a 4-layer PNPN SCR structure. SCR turns on and actually causes VDDshort circuit to ground.
Since all of these MOS devices are located on a monolithic chip, parasitic SCR devices may turn on when the appropriate external stimulus is present, which is common in poorly designed CMOS circuits. Figure 6 is a simplified cross-sectional view of two transistors, one PMOS and one NMOS; they can be connected together for use as logic gates, or as analog amplifiers, or as switches. Parasitic bipolar transistors are responsible for latching, Q1 (vertical PNP) and Q2 (lateral NPN), as shown in the figure below.
Figure 6. Cross-sectional view of PMOS and NMOS devices, including parasitic transistors Q1 and Q2
Of course, suitable design methods can be used to reduce the chance of SCR formation, including increasing the spacing between NMOS and PMOS devices, and inserting highly doped regions between and around NWELL and PWELL. Both layout methods attempt to reduce the ß of a vertical PNP or lateral NPN parasitic bipolar transistor to less than 1. Some of these methods also tend to lower RPWELLand RNWELLresistance, thereby increasing the minimum trigger current required to turn on the SCR.
question:
1. What is the difference between SCR and ordinary rectifier diode? You can find the answer on the Student Zone forum.
About the Author
Doug Mercer graduated from Rensselaer Polytechnic Institute (RPI) in 1977 with a bachelor’s degree in electrical engineering. Since joining Analog Devices in 1977, he has contributed directly or indirectly to more than 30 data converter products and holds 13 patents. He was named an ADI Fellow in 1995. In 2009, he transitioned from full-time employment and continued as an honorary researcher as an ADI consultant, writing for the Active Learning Initiative. In 2016, he was appointed as an engineer-in-residence of the RPI ECSE department.
Antoniu Miclaus is currently a systems applications engineer at Analog Devices, working on ADI teaching projects, as well as Circuits from the Lab®, QA automation and process management to develop embedded software. He joined Analog Devices in February 2017 in Cluj-Napoca, Romania. He is currently a Master of Science student in the Master of Software Engineering program at Babes Bowyer University and holds a Bachelor of Science in Electronics and Telecommunications Engineering from the Technical University of Cluj-Napoca.
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