“pic microcontroller, presumably everyone is familiar with it. Among them, the introduction of pic MCU, the advantages of pic MCU and the insufficiency of pic MCU are all entry-level knowledge. This article will introduce to you the advanced application of pic microcontroller – using the data memory RAM of the pic microcontroller as a register. This article has certain difficulties, and I hope you will study it carefully.
pic microcontroller, presumably everyone is familiar with it. Among them, the introduction of pic MCU, the advantages of pic MCU and the insufficiency of pic MCU are all entry-level knowledge. This article will introduce to you the advanced application of pic microcontroller – using the data memory RAM of the pic microcontroller as a register. This article has certain difficulties, and I hope you will study it carefully.
PIC16C5X uses data memory RAM as registers to make addressing simple and clear, and their functions can be divided into operation registers, I/O registers, general registers and special function registers. Their organizational structure is shown in the figure below: These registers are represented by codes F0 to F79. F0-F4 are operation registers, F5-F7 are I/O registers, and the rest are general-purpose registers. The special function register addresses are opaque to the user.
1. Operation register
1. F0 intermediate address register
Addressing F0 actually means indirect addressing. The actual address is the content of register selection register F4.
Example: MOVLW 10
MOVWF f4 ;10→f4
MOVWF f0 ;55→f10
2. F1 real-time clock/count register (RTCC)
This register is an 8-bit counter. Like other registers, it can be read and written by the program. It is used to count pulses applied to the RTCC pin, or to count the internal clock (acting as a timer).
It can be seen from the above figure that the working state of RTCC is controlled by the OPTION register. The RTS bit of the OPTION register is used to select the counting signal source of RTCC. When RTS is “1”, the signal source is the internal clock, and when RTS is “0”, The signal source is an external signal from the RTCC pin. The PSA bit of the OPTION register controls the prescaler (Prescaler) allocation object. When the PSA bit is “1”, the 8-bit programmable pre-assignment to RTCC, that is, the external or internal signal is divided by the prescaler and then output to RTCC . The frequency division ratio of the prescaler is determined by PS0 to PS2 in OPTION. At this time, the instructions involving writing to the f1 (RTCC) register will clear the prescaler at the same time. However, it should be noted that the content of the OPTION register remains unchanged, that is, the allocation object, frequency division ratio, etc. remain unchanged. The RTE bit of OPTION is used to select the external count pulse trigger edge. When RTE is “1”, it is a falling edge trigger, and when it is “0”, it is a rising edge trigger.
The RTCC counter is counted in an incrementing manner. When the count reaches FFH, after the next count occurs, it will automatically reset to zero and start counting again, and the cycle continues. The RTCC’s response delay time to its input pulse signal is 2 machine cycles, whether the input pulse is an internal clock, an external signal, or the output of a prescaler.
The sampling period of RTCC to external signal is 2 oscillation periods. Therefore, when the prescaler is not used, the pulse width applied to the RTCC pin shall not be less than 2 oscillation cycles, that is, 1/2 instruction cycle.Similarly, when the prescaler is used, the output pulse of the prescaler
The pulse cycle must not be less than the instruction cycle, so the maximum input frequency of the prescaler can reach N.fosc/4, and N is the frequency division ratio of the prescaler, but it must not be greater than 50MHz.
When RTCC uses the internal clock signal, if there is no prescaler, the RTCC value increases by 1 with the instruction tick. When a value is written to RTCC, the value of RTCC will not change in the next two instruction beats, and it will only increase from the third instruction beat, as shown in the figure below.
It should be noted that although the PIC does not have strict requirements on the signal width applied to the RTCC signal terminal externally, if the high level or low level is maintained for too short time, the RTCC may not detect this signal. Generally, the signal width is required to be greater than 10nS.
3. F2 program counter (PC)
The program counter PC can address up to 2K of program memory. The following table lists the PC length and stack length for various PIC16C5X variants.
When the microcontroller is reset (RESET), the value of F2 is all set to “1”. Unless an address jump instruction is executed, after executing an instruction, the F2 (PC) value will increase by 1 to point to the next instruction.
The following commands may change the value of PC:
a. “GOTO” instruction. It can directly write (change) the lower 9 bits of the PC. For the PIC16C56/57/58, the two bits PA1 and PAO of the status register F3 will be placed in the highest two bits of the PC. The “GOTO” instruction shown can jump to anywhere in program memory.
b. “CALL” instruction. It can directly write the lower 8 bits of the PC and clear the 9th bit of the PC at the same time. For PIC16C56/57/58, the two bits PA1 and PAO of status register F3 will be placed in the highest two bits (10th and 11th bits) of the PC.
c. “RETLW” instruction. It writes the value of the stack entry (stack 1) to the PC.
d. “MOVWF F2” instruction. It places the contents of the W register into the PC.
e. “ADDWF F2” command. It adds 1 to the PC value and then adds it to the value of the W register, and writes the result to the PC.
In b, d and e above, bit 9 of the PC is always cleared to zero. Therefore, when using these three instructions to generate program jumps, place the subprogram or branch program at the upper address of each page (000-0FF, 200-2FF, 400-4FF, 600-6FF respectively).
4. F3 status register (STATUS)
F3 contains the arithmetic state, RESET state, program memory page address, etc. of the ALU. Except for the two bits of PD and TO in F3, other bits can be set or cleared by instructions. Note that when you execute an instruction that changes the F3 register, what happens in F3 may surprise you.
Example: CLRF F3; clear F3 to zero
The result you get is F3=000UU100 (U is unchanged) instead of all zeros as imagined. The two bits of UU are PD and TO, which remain unchanged, while 2 bits are set to “1” due to the clearing operation. So if you want to change the content of F3, it is recommended that you use the three instructions BCF, BSF and MOVWF, because their execution does not affect other status bits.
Example: MOVLW 0;0→W
MOVWF F3 ; Clear all the bits of F3 except PD and TO, then you can get F3=000UU000.
For the influence of each instruction on the status bits, please refer to the introduction in Chapter 2.
In addition operation (ADDWF), C is the carry bit. In subtraction (SUBWF), C is the inverse of borrow (Borrow).
Example: CLRF F10 ;F10=0
MOVLW 1 ; 1→W
SUBWF F10 ;F10-W=0-1=FFH→F10
C=0: The result of the operation is negative
Example: MOVLW 1 ;1→W
MOVWF F10 ;F10=1
SUBWF F10 ;F10-W=1-0=1→F10
C=1: The result of the operation is positive
The two bits PD and TO can be used to determine the reason for the RESET. For example, it is judged that RESET is caused by power-on of the chip, or by the overflow of the watchdog WDT time, or by adding a low level to the reset terminal, or by WDT waking up SLEEP.
Table 1.4 lists the events that affect the TO and PD bits. Table 1.5 lists the TO, PD bit states after various RESETs.
It is sometimes necessary to determine where the RESET originated. For example, when initializing the system, it is often necessary to judge whether the reset is caused by power-on. If it is not a power-on reset, no initialization is performed.
The functions of the page selection bits PA1 and PA0 have been described above. When RESET, the PA0-PA2 bits are cleared to zero, so the program area page is automatically selected at page 0 after reset.
5. F4 register selection register (FSR)
Bits 0-4 of F4 are used to select 32 data registers in indirect addressing. Bits 5-7 are read-only bits and are always 1. Please refer to the F0 register description.
The FSR “6:5” bits are used to select the current data register bank (Bank). The PIC16C57 has 80 data registers, as shown in Figure 1.4. The 80 registers are divided into 4 banks (Bank0 to Bank3), and the physical location of the lower 16 registers of each bank is the same (refer to the description of §1.5.3 general-purpose registers). When the 4th bit of FSR is “1”, a certain register with the highest 16 in a certain register bank should be selected according to the FSR “6:5” bits.
Note: When the chip is powered on reset, FSR “6:5” is indeterminate, so it may point to any Bank. Other resets keep the original value unchanged.
2. I/O register
PIC16C52/54/56/58 has two I/O ports RA, RB (F5, F6), PIC16C55/57 has three I/O ports RA, RB, RC (F5, F6, F7). Like other registers, they can be read and written by instructions. They are programmable bidirectional I/O ports, which can be programmed to determine the input/output status of each I/O port.
After RESET, all I/O ports are set to input state (equal to high-impedance state), that is, I/O control registers (TRISA, TRISB, TRISC) are all set to “1”.
1. F5 (A port)
4-bit I/O port register. Only its lower 4 bits can be used. The upper 4 bits are always defined as “0”.
2. F6 (B port)
8-bit I/O port register.
3. F7 (C port) for PIC16C55/PIC16
C57, it is an 8-bit I/O port register.
For PIC16C54/56/58 it is a general purpose register.
§1.5.3 General purpose registers
08H-0FH: Common general registers (addressable without bank selection).
10H-1FH: General purpose registers for Bank0
20H-2FH: Physically equivalent to 00H-0FH.
30H-3FH: General purpose registers of Bank1
40H-4FH: Physically equivalent to 00H-0FH.
50H-5FH: General purpose registers of Bank2
60H-6FH: Physically equivalent to 00H-0FH.
70H-7FH: General purpose registers for Bank3.
3. Special function register
1. Working register (W)
W is used to store the second operand in a two-operand instruction, or for internal data transfers. The arithmetic logic unit ALU connects W and the register, and the operation result of the ALU can be sent to W for storage through the total data bus.
2. I/O control registers (TRISA, TRISB, TRISC)
TRISA, TRISB, and TRISC correspond to I/O ports A, B, and C, respectively. Among them, TRISA has only 4 bits, corresponding to port A. Execute the “TRIS f” instruction to put the value of W into the I/O control register to define the input/output state of each I/O terminal. When “1” is written, the corresponding I/O terminal is set to the input state (high impedance state), and when “0” is written, the corresponding I/O terminal is set to the output state. The I/O control registers are all write-only registers, which are automatically set to all “1” after RESET, that is, all I/O ports are in the input state.
3. Preset multiple/RTCC selection register (OPTION)
OPTION can be used for:
a. Define the prescaler parameters of the prescaler.
b. Assign a prescaler (Prescaler) to RTCC or WDT. Note that the prescaler can only be assigned to either RTCC or WDT, not both.
c. Define the signal source of RTCC.
d. Define the trigger edge of the RTCC signal source (rising edge trigger or falling edge trigger).
When the prescaler is assigned to the RTCC, all instructions that write to the RTCC register such as CLRF 1, MOVWF 1, etc. will clear the prescaler. Similarly, when assigned to the WDT, instructions such as CLRWDT and SLEEP will clear the prescaler to zero.
By executing the “OPTION” instruction, the W value can be placed in the OPTIOW register, and OPTION is set to all “1” after RESET.