“The computer system is based on the microprocessor. Each device must be connected to the microprocessor and must work in coordination. Therefore, the concept of a bus is introduced into the microprocessor. Each device shares the bus, and there can only be one device at any time. Transmit data (multiple devices can receive data at the same time).
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1. Overview of the bus
The computer system is based on the microprocessor. Each device must be connected to the microprocessor and must work in coordination. Therefore, the concept of a bus is introduced into the microprocessor. Each device shares the bus, and there can only be one device at any time. Transmit data (multiple devices can receive data at the same time).
The bus of the computer is divided into three types: control bus, address bus and data bus. The data bus is used to transmit data, the control bus is used to transmit control signals, and the address bus is used to select memory cells or peripherals.
Second, the three-bus structure of the microcontroller
51 series single-chip microcomputer has a perfect bus interface sequence, which can expand the control object, and its direct addressing capability reaches 64k (2 to the 16th power). In the bus mode, different objects share the bus, independently address, time-division multiplexing the bus, the CPU selects the object to be accessed through the address, and completes the information transfer with each object.
The schematic diagram of the three-bus expansion of the single-chip microcomputer is shown in Figure 1.
1. Data bus
51 The data bus of the single-chip microcomputer is the P0 port, and the P0 port is a bidirectional data channel. The CPU sends and reads data from the P0 port.
2. Address bus
The address bus of the 51 series microcontroller is 16 bits.
In order to save the chip pins, the P0 port multiplexing method is adopted. In addition to being used as a data bus, under the timing matching of the ALE signal, through the external data latch, the lower 8-bit address is sent from the P0 port in the first half cycle of the bus access, and then 8-bit data is sent from port P0 in half cycle.
The high 8-bit address is sent through the P2 port.
3. Control bus
The control bus of the 51 series microcontroller includes the read control signal P3.7 and the write control signal P3.6, etc., which are used as enable signals for data read and data write in bus mode respectively.
3. MCU bus timing analysis
51 microcontroller bus timing shown in Figure 2.
As can be seen from Figure 2, the operation cycle to complete a bus (read and write) is T, and the P0 port is time-multiplexed. During the T0 period, the P0 port sends the lower 8-bit address, and the data is latched on the falling edge of ALE and sent out. Low 8-bit address signal. During T1, the P0 port is used as a data bus to send or read data, and the read and write operations of data are completed during the low level period of the read and write control signals.
It should be noted that during the valid period of the control signal (read and write signals), the P2 port sends out the high 8-bit address, and cooperates with the low 8-bit address output by the data latch to realize a 16-bit address bus, that is, the search within the range of 64kB. site.
Since it is impossible for the CPU to perform read and write operations at the same time, it is impossible for the read and write signals to be active at the same time.
Fourth, common single-chip addressing circuit
1. Simple address extension
51 The P2 port of the microcontroller can be directly used as a high-order 8-bit address bus. In some simple system circuits, the P2 port is often used to directly address the drive.
The following uses the data buffer 74LS273 to drive the digital Display as an example to analyze the design of the static digital Display circuit driven by the P2 port addressing.
A LED digital display unit circuit is shown in Figure 3.
WR is in phase with A8 (P2.0) or provides the clock signal of 74LS273. When the “MOVX @DPTR, A” instruction is executed, the address information is determined by the DPTR register, and a valid write signal WR will appear. 0”, the write signal can be input as the clock signal of 74LS273 to complete the data latch.
The P2 port is the 8-bit address line of A8~A15, which can be easily extended to 8 LED digital tubes. The WR signal is connected with A8~A15 by OR relationship, and each address line is active at low level, which can realize 8 LED digital tubes. valid address.
The circuit of this scheme is simple, but the number of effective addresses is too small to be suitable for complex system design.
2. Low 8-bit address latch
The usual design circuit is to use the 8D latch 74LS373 to realize the address latch. The 74HC573 has the same logic function, but the pin layout is different. It is easier to use the 74HC573 for wiring.
The 74LS373 truth table is shown in Figure 4.
When the output enable OE is L and the control enable LE is H, the output is in the following state; when OE is L and LE is L, the output is in the hold state.
The address latch circuit is shown in Figure 5. OE is grounded, and LE is connected to the ALE pin of the microcontroller to generate a low 8-bit address signal that meets the timing.
Executing the following three instructions will result in the timing diagram shown in Figure 6.
MOV DPTR, # 0FF55H; the lower 8-bit address is 55H
MOV A, # 0AAH; data to be sent 0AAH→A (55H inversion)
MOVX, @DPTR, A; 0AAH in A will be sent to the object whose address is 0FF55H.
As can be seen from Figure 6, the P0 port first sends 55H, and the address is latched on the falling edge of ALE, and then the data 0AAH is sent. During the WR valid (low level), the latch outputs the lower 8-bit address 55H, and the P0 port sends data. 0AAH.
3. Complex address interface circuit with decoder
Theoretically, the upper 8-bit address lines can generate 256 valid addresses. How to realize address “expansion”? The exact description of address expansion is address decoding. For example, 3 address lines can be decoded into 8 addresses, and 4 can be decoded into 16 addresses. a valid address. Here, 3-8 decoders are selected to implement address decoding. The circuit diagram and corresponding addressing are shown in Table 1.
5. Example of MCU bus addressing circuit
A single-chip microcomputer system with bus expansion interface, including external 32k RAM expansion, LCD1602 interface, and input and output ports.
D0~D7 are connected to the data bus P0 port, the address lines A0~A14 are connected to the lower 15 bits of the address bus of the microcontroller, and the address line A15 of the microcontroller is connected to the RAM chip select signal, and the low level is valid, so that the RAM address allocation is from 0000H to 7FFFH, and 74138 is decoded. The addresses do not conflict.
The LCD1602 interface circuit is shown in Figure 9.
RS and RW are connected to A12 and A13 respectively, and the address of the enable signal is Y7, so that the four drive addresses of the LCD (data read and write and command read and write) are 0CFFFH to 0FFFFH (don’t care bit is 1) or 8700H to 0B700H (don’t care bit is 0).
Sometimes the pins of the single-chip microcomputer are not enough and need to be expanded. The input port expansion circuit is shown in Figure 10.
Using the high-impedance state function of 74HC573 (74LS373), connect its output Q0~Q7 to P0 port, and in satisfying the bus address read operation, the data input into InPORT can be read into the accumulator of the single-chip microcomputer, and the address is 0F8FFH or 8000H.
The output port expansion circuit is shown in Figure 11.
Using the data latch function of 74LS273, in meeting the bus address write operation, the data in the accumulator of the single-chip microcomputer can be written into the 273 latch output, and the address is 0F8FFH or 8000H. Since the control bus used is different, the address can be shared with the input.
6. Conclusion
Bus expansion is a technology that must be mastered in designing single-chip control circuits. A large number of special function ICs support bus interfaces, such as ADC0809, TLC7528, DDS device AD9851, etc.
The main point of the bus interface is that the bus is time-multiplexed under strict control timing to realize complex system design.
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